The present invention generally relates to mitigating pattern collapse of ultra-thin resists. In particular, the present invention relates to an etch of a hardmask immediately after developing an ultra-thin resist, and control thereof.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This includes the width and spacing of interconnecting lines and the surface geometry such as corners and edges of various features. Since numerous interconnecting lines are typically present on a semiconductor wafer, the trend toward higher device densities is a notable concern.
The requirement of small features, such as metal lines, with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist, and an exposing source (such as optical light, X-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the photomask, for a particular pattern. The lithographic coating is generally a radiation-sensitized coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive of the subject pattern. Exposure of the coating through the photomask causes a chemical transformation in the exposed areas of the coating thereby making the image area either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. However, lithography is not without limitations. Patterning features having dimensions of about 0.25 xcexcm, 0.18 xcexcm or less with acceptable resolution is difficult. This is because photoresist layers used in lithography typically have thicknesses on the order of 7,000 xc3x85 and higher. Such relatively thick photoresist layers are not conducive to making small patterned dimensions with good resolution.
Using relatively thin photoresists (such as less than about 5,000 xc3x85) enables the patterning of smaller and smaller dimensions. However, insufficient resistance to pattern collapse during post-development rinse and dry cycles is associated with using thin photoresists. Insufficient resistance to pattern collapse is also associated with smaller and smaller pitches (of patterned photoresists). The relatively thin patterned photoresists simply do not withstand the physical strain imposed by the post-development rinse and dry steps. For example, pattern collapse due to water rinse, dry cycles, and spinning action associated with such steps, result in poor pattern transfer. In many instances the relatively thin patterned photoresists are destroyed or partially destroyed during deionized water rinsing. Improved lithography procedures providing improved resolution and improved resistance to pattern collapse are therefore desired.
The present invention generally provides systems and methods that mitigate the problems associated with pattern collapse, improve critical dimension control and/or improve resolution when using ultra-thin resists. Since it is possible to mitigate the problems associated with ultra-thin photoresist pattern collapse, the present invention provides improved methods for processing layers underneath ultra-thin photoresists including metal layers, dielectric layers, and silicon layers. The methods of the present invention make it possible to consistently process underlying layers through trenches, holes and other openings on the order of about 0.18 xcexcm or less in size. As a result, the present invention effectively addresses the concerns raised by the trend towards the miniaturization of semiconductor devices.
In one embodiment, the present invention relates to a semiconductor processing system containing a processing chamber coupled to a measurement system and a control system and operable to develop an ultra-thin resist and etch a hardmask; a supply of a developer for contact with the ultra-thin resist; a supply of an etch solution; the measurement system for in situ monitoring of patterning the ultra-thin resist and the hardmask and for providing a measurement signal indicative of the measured patterning; and the control system for controlling treatment parameters within the chamber including contact time of the etch solution with the patterned resist and hardmask. The control system adjusts the treatment parameters to control patterning based on the measurement signal.
In another embodiment, the present invention relates to a method of processing an ultra-thin resist, involving depositing the ultra-thin resist over a hardmask layer that is over a semiconductor substrate; irradiating the ultra-thin resist; developing the ultra-thin resist with a developer to form a patterned resist, wherein the ultra-thin resist is not dried; optionally rinsing the patterned resist with water, and etching the hardmask layer with an etch solution within about 1 minute after developing to provide a patterned hardmask. The method may further include controlling treatment parameters using a control system and a measurement system.